The present invention relates generally to integrated circuit devices, and more specifically to a clock pulse extender mode for clocked memory devices having precharged data paths.
High speed clocked memory devices can often enhance their overall memory access delay time by using precharged data path techniques for both the address decode path and the data sense/output path of a memory device. Examples of memory devices include, but are not limited to, random access memories (RAMs), static random access memories (SRAMs), and burst mode RAMs (BRAMs). Use of these precharged data path techniques increases effective gate fanout for the data path (or address decode path) of the high speed clocked memory device. Implementation of these techniques often requires that the address decode path and/or the data sense/output path of the memory device be precharged (or preset) to a known state, typically inactive, prior to allowing new data such as address inputs or array data entry into the precharged path. Input entry into the address decode path or the data sense/output path is often gated by a pulsed path active strobe that has a pulse width of self-timed duration. After the pulsed path active strobe becomes inactive, a reset (or precharge) strobe is applied to the path stages in a parallel manner to return the path to its inactive state. The minimum clock period for this type of precharged data path is equal to the data delay through the path plus the path precharge time.
From the above description it can be seen that a small self-timed pulse width for both the pulsed path active strobe and the reset strobe is desirable for a high speed clock cycle in order to obtain the minimum clock period of the memory device. Conversely, the width of the self-timed strobes must also be of long enough duration to allow the active data path to resolve, i.e. to stabilize to an appropriate state in response to an input stimulus such as an input address, and and to fully return the inactive data path to the proper initial condition.
These self-timed pulses of the pulsed path active strobe and the reset strobe are often generated using a gate delay timing chain. The pulse duration of these self-timed pulses may be subject to large variation. This may be especially the case where the gate delay timing chain of a high speed clocked memory device is designed using a complementary metal oxide semiconductor (CMOS) process and large variations of the width of self-timed pulses may be due to process parameter variations, voltage variations, and external temperature bias. This inherent pulse width variation of the self-timed pulses makes it difficult to both make the timed pulse criteria of long enough duration for correct circuit action while making it of minimum width in order to achieve maximum clock frequency. When the circuit under design is completely new, or being designed to a new process, or both, it is advantageous to have a method which will enable the design to be verified even if the self-timed pulse width variation is more than anticipated.